EVALUATING PERFORMANCE OF CHIP MULTI-CORE WITH CACHE LEVEL

Abstract

Chip multi-core (CMP) is applied widely in high performance computer systems
and supper computers. The performance of CMP with application of cach multi-level
structure is interested by many researchers. There are many solutions used to
evaluate the performance of MCP. In this paper, the authors build equipvalent
circuuit, closed form and calculating the performance parameters based on
MCPFCQN. The performance evaluation of CMP is characterised by 05 parameters:
number of jobs, waiting time, response time, utilization and capacity. The results
show that when the number of caches increases, number of jobs, waiting time,
utilization and capacity are increased too, but response time is deacreased