COMPENSATION TECHNIQUE FOR CAPACITOR-LESS LDO IN CMOS

Abstract

This paper presents a compensation technique for stable operation of
capacitor-less low-dropout Regulator (LDO) circuits for System on Chip (SoC)
applications and embedded systems. Based on the analysis of compensation
methods using Miller capacitor and using capacitor in combination with
feedback resistors, the paper proposes to combine these two compensation
methods to achieve high phase margin (PM) and expand Gain-bandwidth
(GBW). The combination of these two compensation techniques obtain both fast
recovery time during load step and high Power supply rejection ratio (PSRR). The
proposed LDO is implemented in a 180nm CMOS process. The simulation results
demonstrate that the LDO has a short recovery time of 300ns and 500ns for load
transient from 10µA to 100mA and vice versa, respectively. The PSRR at 1kHz,
100kHz and 10MHz are 58.5dB, 34.2dB and 5.8dB, respectively.