Designing and simulation a 15-bit successive approximation register analog-to-digital converter

  • Duy Phong Pham Faculty of Electronics and Telecommunication Engineering, Electric Power University;
  • Thanh Pham Xuan Faculty of Electronics Engineering, Ha Noi University of Industry
  • Nguyen Thi Viet Ha Faculty of Electronics Engineering, Ha Noi University of Industry
  • Manh Kha Hoang Faculty of Electronics Engineering, Ha Noi University of Industry
Keywords: Analog-to-digital converters; Successive approximation register; Binary weighted with attenuation capacitor.

Abstract

Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.

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Published
2023-05-25
Issue
Vol. 87 (2023)
Section
Overview