A highly linear wide bandwidth down-conversion mixer for direct-conversion receivers in CMOS

Abstract

 This paper presents the down-conversion mixer in the direct-conversion receivers for new generation communication systems such as LTE and sub-6 GHz 5G. A current-controlled dual-balanced passive mixer combines with a local oscillator (LO) signal that positive pulse width is 1/4 the signal cycle (25% duty cycle) to reduce noise and improve conversion gain. A transimpedance amplifier (TIA) circuit based on a self-bias current-reuse inverter circuit is proposed to achieve high linearity and wide bandwidth simultaneously. The mixer is designed on 28 nm CMOS technology. Post-layout simulation results illustrate that the mixer has a conversion gain variation of 0.45 dB per 100 MHz in a baseband bandwidth of 580 MHz. The noise figure (NF) is 9.2 dB. The two-order input intercept point (IIP2) and the three-order input intercept point (IIP3) is 23.6 dBm and 61.5 dBm, respectively. The circuit consumes power of 40.1 mW with a supply voltage of 0.9 V whereas it occupies an area of ​​0.023 mm².