Proposed early-stopping algorithm for the FPGA implementation of a Min-Sum decoder for NB-LDPC codes

Abstract

This paper proposes an early-stopping algorithm applied to the design of a Min-Sum decoder for NB-LDPC (32,16) codes on FPGA. The decoder is implemented in SystemVerilog for NB-LDPC codes over GF(16) and evaluated on AWGN channels with performance metrics including bit error rate (BER), frame error rate (FER), average iteration count, and decoding latency. The early-stopping algorithm is integrated into the loop control block to terminate the decoding process as soon as convergence is achieved, thus reducing the average number of decoding iterations. Implementation results show that the average decoding latency is reduced to 134.4 ns, corresponding to BER ≈ 5.31 × 10⁻³ and FER = 0.12, consistent with reference MATLAB simulations. These results demonstrate that implementing NB-LDPC coding and decoding algorithms on FPGA, combined with an appropriate early-stopping mechanism, can significantly reduce hardware processing time, enabling real-time communication applications.