Performance and Memory Trade-offs in SM4 Implementation on Embedded ARM Cortex-M Microcontrollers

Abstract

The SM4 block cipher has been widely adopted in security applications across embedded systems, particularly as part of China’s national cryptographic standards. However, its practical deployment on resource-constrained microcontrollers remains challenging due to limited processing power and memory. This paper investigates the trade-offs between performance and memory usage in various SM4 software implementations on ARM Cortex-M microcontrollers. We evaluate and compare three implementation strategies: (1) S-box lookup tables stored in Flash and SRAM, (2) T-table optimization that combines substitution and transformation operations, and (3) direct computation of the S-box using Galois Field (GF) logic. Each implementation is benchmarked on a 32-bit STM32 microcontroller to measure encryption latency, SRAM and Flash memory usage, and code complexity. The results reveal that the T-table implementation in SRAM provides the best performance with the lowest encryption latency, albeit at the cost of high SRAM consumption. Conversely, the GF logic implementation minimizes memory usage but suffers from the slowest execution time. This study provides important insights for selecting the most suitable SM4 implementation strategy for embedded systems with varying resource constraints and real-time requirements.