GAAFETs and 2D materials for sub-3 nm nodes: performance, fabrication challenges, and integration strategies

Abstract

This paper investigates the transition from FinFETs to Gate-All-Around Field-Effect Transistors (GAAFETs) as a strategic advancement for CMOS technology nodes beyond 3 nm, with a focus on performance enhancements, fabrication challenges, and integration strategies. We conduct a comparative analysis of state-of-the-art transistor architectures—namely TSMC’s 3 nm FinFET, Samsung’s 3 nm nanosheet GAAFET (MBCFET™), and Intel’s upcoming 20A RibbonFET—to highlight the superior electrostatic control and drive current offered by GAAFETs. The role of emerging materials such as SiGe, III–V compounds, and two-dimensional (2D) semiconductors (e.g., monolayer MoS₂ and WSe₂) is examined in the context of extending transistor scaling into the sub-1 nm regime, particularly with respect to their potential to mitigate short-channel effects. We further address key fabrication challenges associated with sub-3 nm technologies, including the limitations of extreme ultraviolet (EUV) lithography, the need for atomic-scale process control, and escalating production costs. In addition, we explore heterogeneous integration techniques, such as chiplet-based design and 3D stacking, as complementary approaches to sustain performance scaling. Finally, we discuss prospective post-GAAFET device architectures—including Complementary FETs (CFETs) and Vertical Transport FETs (VTFETs)—emphasizing the necessity of cross-disciplinary innovation to uphold the trajectory of Moore’s Law. The findings present a comprehensive perspective on semiconductor scaling in the "<3 nm" era, balancing trade-offs between performance, energy efficiency, and manufacturability.