A NOVEL METHODOLOGY TO IMPROVE POWER CONSUMPTION FOR ADDERS

Abstract

Adders are one of the important components of forming a computational system. Optimizing power consumption, speed and delay of adders has contributed to the economical and efficient use of energy. This paper proposes a general flow to implement the combinational logic circuits using Null Convention Logic (NCL) for asynchronous circuits. Carry Look Ahead (CLA) adder and Ripple Carry Adder (RCA) are chosen in order to illustrate the proposed flow. These adders are implemented by DC tool using conventional cell libraries. In addition, we also make the comparison of the implemented results of adders above by asynchronous and synchronous techniques. The synthesis results indicate that the power of the NCL designs decreases by 62.88% (RCA), and 75.09% (CLA) compared to the Boolean logic combinational designs.